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NXP Semiconductors
LPC11C12/C14
11. Application information
11.1 ADC usage notes
The following guidelines show how to increase the performance of the ADC in a noisy
environment beyond the ADC specifications listed in Table 6 :
? The ADC input trace must be short and as close as possible to the LPC11C12/C14
chip.
? The ADC input traces must be shielded from fast switching digital signals and noisy
power supply lines.
? Because the ADC and the digital core share the same power supply, the power supply
line must be adequately filtered.
? To improve the ADC performance in a very noisy environment, put the device in Sleep
mode during the ADC conversion.
11.2 XTAL input
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
C i = 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground C g which attenuates the input voltage by a factor C i /(C i + C g ). In slave
mode, a minimum of 200 mV(RMS) is needed.
LPC1xxx
XTALIN
Ci
Cg
100 pF
002aae788
Fig 22. Slave mode operation of the on-chip oscillator
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
( Figure 22 ), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This
corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.
The XTALOUT pin in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in Figure 23 and in
Table 15 and Table 16 . Since the feedback resistance is integrated on chip, only a crystal
and the capacitances C X1 and C X2 need to be connected externally in case of
fundamental mode oscillation (the fundamental frequency is represented by L, C L and
R S ). Capacitance C P in Figure 23 represents the parallel package capacitance and should
not be larger than 7 pF. Parameters F OSC , C L , R S and C P are supplied by the crystal
manufacturer (see Table 15 ).
LPC11C12_C14_0
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 00.05 — 23 April 2010
? NXP B.V. 2010. All rights reserved.
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